Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as communication and multimedia programs. A processing system for such products may include multiple processors, complex memory systems including multi-levels of caches and memory for storing instructions and data, controllers, peripheral devices such as communication interfaces, and fixed function logic blocks configured, for example, on a single chip.
Multiple processors (MPs), such as a dual processor or a quad processor, are generally designed as a shared memory system utilizing a multi-level memory hierarchy. In such a shared-memory MP, data may be organized as private data and shared data. The private data is further organized for use locally by each processor in the MP. The shared data requires a mechanism to efficiently communicate data among the processors and to efficiently maintain coherence of the data between the processors. One mechanism to efficiently communicate data among the processors is to use a coherent bus, within the multi-level memory hierarchy, which supports a coherent protocol to ensure data that is shared is consistent between each of the processors.
For example, a bus may be used at a cache level that requires coherence of the shared data, such as at a level 2 cache position in the shared memory hierarchy. The coherent bus is utilized between each level 2 cache associated with each processor in the MP. Various protocols have been developed to maintain consistency of data that is shared, such as the modified owned exclusive shared Invalid (MOESI) protocol. In the MOESI protocol, each cache line is tagged in such a way as to indicate whether the cache line is present only in the current cache and is dirty (modified), the cache line is present only in the current cache and is clean (exclusive), the cache line may be stored in other caches in the MP and is dirty in the present cache (owned), the cache line may be stored in other caches in the MP and is clean in the present cache (shared), the cache line is invalid in the present cache (invalid). The MOESI states are checked whenever a cache line is written to in order to determine the effect of that write on the corresponding data shared in the multiple caches.
In a multi-processor, specialized instructions are used by each processing agent for semaphore management. Semaphore management often involves a pair of specialized load and store instructions to read a memory location, set a reservation granule, and conditionally write the memory location based on the state of the reservation granule. Systems that maintain cache coherence across a bus have the potential for these semaphore management instructions to result in live-lock or poor performance, if two or more processors are competing for the same semaphore.